Rakuten Symphony will have new Distributed Units (DUs) featuring Intel SoCs with integrated L1 acceleration available from Q2 next year, according to CEO Tariq Amin. He said the products would be a “massive game changer” by enabling Open RAN architectures for complex, brownfield operations at new cost and performance points.
Amin said, “Rakuten Symphony already has engineering samples of Intel’s new CPU, and I would like to commercialize one variant of this platform in Q2 next year with a higher capacity variant in Q3/Q4 next year. We already did the design – I think it is a breakthrough. We have locked in all the elements and next week we will begin an RFP selection for a contract manufacture of who will build this product.”
Rakuten Symphony already has Symware – an 18kg, outdoor DU with integrated FEC acceleration, timing, eCRPI conversion and virtual cell site router that can be located at a cell site rather than in an edge data center, but Amin said that the new Symware 2.0 design will go beyond that in terms of power and cost efficiency, with 4x performance over the previous generation.
He will also license the reference design for others to build on.
“I love the idea of having a larger ecosystem to help me increase volumes: volume is good for Intel and for me to lower costs with Intel as well. Whatever reference design we build we will open to the world – not just Rakuten Symphony. We will license certain SW components, they will be cost value negligible, and we will offer that as two variants, one that you can consume a full integrated stack, and one where you buy the platform which is the hardware plus the Host OS and some manageability layer on top of it, and on top of it you could put any application you want.”
As TMN first reported in October, Rakuten Symphony is taking advantage of Intel’s 4th Gen Intel Xeon Scalable Processors with “vRAN boost” – a next generation of product that integrates L1 acceleration on the SoC, rather than plugging in a separate L1 accelerator card. This integrated acceleration reduces power demand and increases performance, Intel and Rakuten Symphony say, to the point where the DU-CU architecture based on a COTS hardware platform becomes deployable in mature, brownfield networks.
Sachin Katti, CTO and CSO, Network and Edge Group, Intel, said that this architecture change will be a “tipping point for vRAN” because it will mean that telcos can achieve a cloud native architecture on a common hardware platform end-to-end , including Layer 1, eliminating costs and enabling greater access to innovation.
He said, “True Open RAN requires a full cloud native architecture end-to-end. If you want the full automation and TCO benefits of cloud native, you need a full cloud platform end-to-end, including Layer 1.”
“The previous architecture needed to have the CPU plus a separate accelerator card to deliver the performance needed for a DU workload. We have listened to feedback from Rakuten Symphony, as well as others in the ecosystem, that this adds complexity. The new processors coming from Intel in Q1/Q2 next year are going to integrate that separate card into the CPU itself, so you now only need one CPU and you get the benefits of a faster CPU as well as the integrated acceleration. That means you can double the amount of spectrum or subscribers you can serve within the same power envelope. Just changing the hardware will not only reduce the number of parts you can have, it will also double the capacity from the previous generation, and you will get an additional 20% saving because of the integrated acceleration.”
Katti listed the benefits of cloud native – evolving hardware and software at different time scales, a more robust ecosystem, automation and lower TCO – but added that these benefits can only be captured if the architecture can deliver the performance that a telco network needs for specific telco workloads.
“And for that we believe that L1 also needs to be cloud native. Otherwise you have a hardware appliance in the middle that is now interacting with the rest of the stack and you are running two different management planes at that point, which loses a lot of the benefits of automation that cloud native brings, and defeats the purpose of going towards full Open RAN deployments.” He added that as interfaces from the RIC and SMO are developed, many of them require changes in the network stack both at L1 and L2. “It’s really hard to do that if part of the stack is baked into the hardware,” he added.
That is why Intel, reacting to customer demands – as well as some public skepticism from some operators – and also a move from other chip providers to develop inline acceleration on ARM-based architectures, has moved to integrate more processing capability within the CPU design.
The tipping point where a general purpose architecture is going to be better than custom ASIC architectures is not very far away
Katti said that advances Intel is making in silicon densification will enable that shift in architecture.
“Really this speaks to where silicon architecture is going to go in the future, which is heterogeneous but single SoCs. So you will have SoCs that combine compute, acceleration and networking into a single die, and deliver all the features needed for a workload without you having to source multiple components from different vendors and deal with the complexity of different platforms.”
A Moore’s Law for vRAN?
“Can we create a Moore’s Law for vRAN? Our goal is to double the performance per Watt with each generation. Eventually we believe that as we keep at this pace, and we are investing in five process nodes in four years and by 2025 we will have the best foundry in the world, that innovation on the design on the SoC means we will be doubling the performance per Watt of every generation of product we deliver for the vRAN workloads. The tipping point where a general purpose architecture is going to be better than custom ASIC architectures is not very far away. So you get the full benefit of a cloud architecture and a software defined network and there is no trade off on performance to get to an Open RAN architecture.”
For brownfield the right architecture that will start a transformation to commoditized hardware is to have the acceleration, 5G instruction sets and CPU cores all integrated into the same die
Rakuten Symphony’s Amin agreed that this tipping point is approaching, even for large brownfield operators who have been notably reluctant to get deep into Open RAN solutions in the main, workhorse parts of the network.
He said, “Rakuten Symphony has been very privileged to work with large global operators to understand the brownfield challenge. The biggest problems these operators face are the complexities in spectrum holding, capacity requirements and carrier aggregation needs to achieve the desired throughput. They can do it with the hardware they have today, but they need a lot more hardware, which increases cost and energy consumption. So we think for brownfield the right architecture that will start a transformation to commoditized hardware is to have the acceleration, 5G instruction sets and CPU cores all integrated into the same die. This is the platform that will deliver better capacity with better performance – a 300% improvement.”
“As an operator, lowest cost per carrier is extremely important, and I will go on the record to say I will validate and prove that this Open RAN architecture will deliver better energy efficiency than a legacy architecture implementation. “
“14-15 months ago we initiated a discussion about Intel’s future roadmap for silicon. And I came to the realization that to really achieve the challenge of fixing the cost and complexity of the DU, it is extremely critical that the integration of discrete components into the same silicon die must happen. So one idea that came about, we reviewed the CPU die architect of their next generation platform, and we thought about a creative idea, why don’t we take the entire acceleration that one needs for 5G radio and complement it in the same CPU die . This is really a novel idea. It’s not built on just pure general purpose cores, the CPU design of tomorrow must include the CPU plus a wrapper of hardware acceleration that we will use for a variety of workloads. We need the specific acceleration to be integrated and with Symware we have identified seven discrete components we want to work with Intel to integrate.”
Amin also said that, as an operator that has “hardened” the Intel FlexRAN platform, it would take a minimum of 18 months to port away from Intel to another platform. That, of course, must also have been a factor in his commitment to Intel’s roadmap. But he insists he has full trust in Intel’s upcoming development to drive the commoditization of Open RAN products, including the DU.